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https://tinyplantnews.com/git2/ldaphotos
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Now accepts argument '-f', for which the argument is a file path. Opens file, then reads input from it. If file is not provided or fopen() fails, ldaphotos defaults to reading message from standard input.
129 lines
4.7 KiB
Makefile
129 lines
4.7 KiB
Makefile
#NEWPROJECT requires refactor.sh sources
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# Taken from https://stackoverflow.com/questions/30573481/how-to-write-a-makefile-with-separate-source-and-header-directories
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# Always build targets and unit tests together. This avoids the scenario wherein the targets are built, then the source files are edited, then the unit tests are built and, accidentally, outdated targets are packaged and shipped. I say this knowing full well that I never ship my targets to anyone ever.
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PREFIX :=
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SUFFIX :=
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SRCDIR := sources
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MAINDIR := $(SRCDIR)/main
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INCDIR := $(SRCDIR)/include
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OBJDIR := objects
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MAINOD := $(OBJDIR)/main
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BINDIR := build
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INSTDIR := /usr/local/bin
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REFACTOR := refactor.h
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TESTCFLAGS:= $(pkg-config --cflags criterion)
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TESTLIBS := $(pkg-config --libs criterion)
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TESTDIR := $(SRCDIR)/test
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TESTOD := $(OBJDIR)/test
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HEADERS := $(wildcard $(INCDIR)/*.h)
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MAINS := $(wildcard $(MAINDIR)/*.c)
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MAINOBJS := $(patsubst $(MAINDIR)/%.c, $(MAINOD)/%.o, $(MAINS))
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TESTS := $(wildcard $(TESTDIR)/*.c)
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TESTOBJS := $(patsubst $(TESTDIR)/%.c, $(TESTOD)/%.o, $(TESTS))
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UNITTESTS := $(patsubst $(TESTDIR)/%.c, $(BINDIR)/%, $(TESTS))
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TARGETS := $(patsubst $(MAINDIR)/%.c, $(BINDIR)/%, $(MAINS))
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SOURCES := $(wildcard $(SRCDIR)/*.c)
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OBJECTS := $(patsubst $(SRCDIR)/%.c, $(OBJDIR)/%.o, $(SOURCES))
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CPPFLAGS := -I$(abspath $(INCDIR)) -MMD -MP -DUSE_LIBNOTIFY -DUSE_SYSLOG
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CFLAGS := -Wall -Werror -Wpedantic $(shell pkg-config --cflags libnotify) -ggdb
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LDFLAGS := #-Lmath or whatever
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LDLIBS := $(shell pkg-config --libs libnotify libcrypto) #-lm or whatever
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define MANGLE =
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$(dir $(1))$(PREFIX)$(notdir $(1))$(SUFFIX)
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endef
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.PHONY: all clean
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all: $(TARGETS) $(UNITTESTS)
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@echo "Executables built: " $^
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refactor:
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./refactor.sh
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$(UNITTESTS): $(OBJECTS) $(TESTOBJS) | $(BINDIR) $(OBJDIR) $(TESTOD)
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@echo "Linking unit tests..."
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@echo "Object files for tests is " $(TESTOBJS)
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$(CC) $(LDFLAGS) $(OBJECTS) $(patsubst $(BINDIR)/%, $(TESTOD)/%.o, $@) $(LDLIBS) $(TESTLIBS) -o $(dir $@)$(PREFIX)$(notdir $@)$(SUFFIX)
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@echo "...Done linking unit tests"
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$(TARGETS): $(OBJECTS) $(MAINOBJS) | $(BINDIR) $(OBJDIR) $(MAINOD)
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@echo "Linking targets..."
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$(CC) $(LDFLAGS) $(OBJECTS) $(patsubst $(BINDIR)/%, $(MAINOD)/%.o, $@) $(LDLIBS) -o $(dir $@)$(PREFIX)$(notdir $@)$(SUFFIX)
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@echo "...Done linking targets"
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$(BINDIR) $(OBJDIR) $(MAINOD) $(TESTOD):
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mkdir --parents $@
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$(OBJDIR)/%.o: $(SRCDIR)/%.c $(HEADERS) | $(OBJDIR)
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$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@
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$(MAINOD)/%.o: $(MAINDIR)/%.c $(HEADERS) | $(MAINOD)
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$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@
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$(TESTOD)/%.o: $(TESTDIR)/%.c $(HEADERS) | $(TESTOD)
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$(CC) $(CPPFLAGS) $(CFLAGS) $(TESTCFLAGS) -c $< -o $@
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# $| evaluates to the order-only prerequisites, in this case: $(TARGETS)
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# The $(foreach ...) function will evaluate to a semicolon-separated list of 'cp <target> $instdir'
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# Putting this $(foreach ...) into the recipe means that its result
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# cp a /usr/local/bin; cp b /usr/local/bin;
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# will be run as a shell command.
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#
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# Shamelessly derived from:
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# https://stackoverflow.com/questions/7918511/make-execute-an-action-for-each-prerequisite
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install: | $(TARGETS)
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@echo "Installing executables to $(INSTDIR)"
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@$(foreach target, $|, cp -v $(call MANGLE, $(target)) $(INSTDIR);)
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uninstall: | $(TARGETS)
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@echo "Removing executables from $(INSTDIR)"
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$(foreach target, $(notdir $(call MANGLE, $|)), rm -v $(INSTDIR)/$(target);)
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clean:
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$(RM) -rv $(BINDIR) $(OBJDIR)
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# Lazy kludge to run the first executable specified in $(TARGETS)
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# Could also be accomplished by running $< but this is easier to read
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run: all
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$(eval MANGLEDNAME=$(call MANGLE, $(word 1,$(TARGETS))))
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@echo "Running " $(MANGLEDNAME)
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@$(MANGLEDNAME)
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# @$(dir $(word 1,$(TARGETS)))$(PREFIX)$(notdir $(word 1,$(TARGETS)))$(SUFFIX)
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# unit testing!
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test: $(TARGETS) $(UNITTESTS)
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@echo "Testing " $(word 1,$(UNITTESTS))
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@$(dir $(word 1,$(UNITTESTS)))$(PREFIX)$(notdir $(word 1,$(UNITTESTS)))$(SUFFIX)
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.PHONY: variable
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variable: all
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$(eval mangle2=$(dir $(word 1,$(UNITTESTS)))$(PREFIX)$(notdir $(word 1,$(UNITTESTS)))$(SUFFIX))
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$(eval mangle3=$(call MANGLE, $(UNITTESTS)))
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@echo "variable declared within a recipe: "$(mangle2)
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@echo "variable declared within a recipe using a canned recipe: "$(mangle3)
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# Honestly still not sure what this directive does.
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# It's an include directive, which processes all .d files that correspond to members of $(OBJ),
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# with the hyphen in front meaning that it suppresses/ignores errors (from nonexistent .d files)
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# Seems to be included under the stipulation that GNU make will auto-generate .d files based on
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# a given file's #include directives?
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# https://stackoverflow.com/questions/19114410/what-is-d-file-after-building-with-make
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-include $(OBJ:.o=.d)
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