78 lines
2.5 KiB
Makefile
78 lines
2.5 KiB
Makefile
#NEWPROJECT requires refactor.sh main.c
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# Taken from https://stackoverflow.com/questions/30573481/how-to-write-a-makefile-with-separate-source-and-header-directories
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SRCDIR := sources
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MAINDIR := $(SRCDIR)/main
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INCDIR := include
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OBJDIR := objects
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MAINOD := $(OBJDIR)/main
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BINDIR := build
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INSTDIR := /usr/local/bin
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REFACTOR := refactor.h
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HEADERS := $(wildcard $(INCDIR)/*.h)
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MAINS := $(wildcard $(MAINDIR)/*.c)
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MAINOBJS := $(patsubst $(MAINDIR)/%.c, $(MAINOD)/%.o, $(MAINS))
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TARGETS := $(patsubst $(MAINDIR)/%.c, $(BINDIR)/%, $(MAINS))
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SOURCES := $(wildcard $(SRCDIR)/*.c)
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OBJECTS := $(patsubst $(SRCDIR)/%.c, $(OBJDIR)/%.o, $(SOURCES))
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CPPFLAGS := -Iinclude -MMD -MP
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CFLAGS := -Wall -Werror -Wpedantic
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LDFLAGS := #-Lmath or whatever
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LDLIBS := #-lm or whatever
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.PHONY: all clean
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all: $(TARGETS)
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@echo $(TARGETS)
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refactor:
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./refactor.sh
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$(TARGETS): $(OBJECTS) $(MAINOBJS) | $(BINDIR) $(OBJDIR) $(MAINOD)
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$(CC) $(LDFLAGS) $(OBJECTS) $(patsubst $(BINDIR)/%, $(MAINOD)/%.o, $@) $(LDLIBS) -o $@
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$(BINDIR) $(OBJDIR) $(MAINOD):
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mkdir --parents $@
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$(OBJDIR)/%.o: $(SRCDIR)/%.c $(HEADERS) | $(OBJDIR)
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$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@
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$(MAINOD)/%.o: $(MAINDIR)/%.c $(HEADERS) | $(MAINOD)
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$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@
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# $| evaluates to the order-only prerequisites, in this case: $(TARGETS)
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# The $(foreach ...) function will evaluate to a semicolon-separated list of 'cp <target> $instdir'
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# Putting this $(foreach ...) into the recipe means that its result
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# cp a /usr/local/bin; cp b /usr/local/bin;
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# will be run as a shell command.
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#
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# Shamelessly derived from:
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# https://stackoverflow.com/questions/7918511/make-execute-an-action-for-each-prerequisite
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install: | $(TARGETS)
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@echo "Installing executables to $(INSTDIR)"
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@$(foreach target, $|, cp -v $(target) $(INSTDIR);)
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uninstall: | $(TARGETS)
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@echo "Removing executables from $(INSTDIR)"
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$(foreach target, $(notdir $|), rm -v $(INSTDIR)/$(target);)
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clean:
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$(RM) -rv $(BINDIR) $(OBJDIR)
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# Honestly still not sure what this directive does.
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# It's an include directive, which processes all .d files that correspond to members of $(OBJ),
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# with the hyphen in front meaning that it suppresses/ignores errors (from nonexistent .d files)
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# Seems to be included under the stipulation that GNU make will auto-generate .d files based on
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# a given file's #include directives?
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# https://stackoverflow.com/questions/19114410/what-is-d-file-after-building-with-make
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-include $(OBJ:.o=.d)
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